FIFO (First In, First Out) or “Queues” are vital components used for buffering and flow control in digital designs. A FIFO typically has storage (e.g., data-path) and associated read and write pointers (control logic). Low-voltage operation through reduction of minimum voltage of operation (VMIN) is an effective approach to reduce power in digital designs. At low supply voltages, logic paths writing to FIFO buffers are susceptible to dynamic variations such as voltage droops or temperature changes which can lead to timing failures. Tolerance to fast transients may be needed to maintain robust FIFO buffer operation.
FIG. 1 shows a conventional implementation 100 of a FIFO, enhanced with error detection sequentials (EDS) at the input to protect FIFO writes, providing dynamic variation tolerance. Implementation 100 consists of a master-slave flip-flop (MSFF) 101 coupled to a latch 102, an XOR gate 103, and a FIFO 104. In this implementation, FIFO 104 is connected in series to the sampling latch 102 such that output Fifo_in of latch 102 is received by FIFO 104. MSFF 101 is used for double sampling of input data ‘D.’ The outputs of MSFF 101 and latch 102 are compared by XOR 103 to determine whether the outputs differ. If the outputs differ, the XOR 103 asserts an Error signal. This conventional implementation 100, however, adds a cycle of latency.